1. Field of the Invention
This invention relates to a peak shift correction circuit for correcting a peak shift for a peak detection signal from a playback signal provided from a magnetic storage medium such as a magnetic tape or a floppy disk and to a magnetic storage medium playback apparatus using the circuit.
2. Description of the Related Art
Currently, with a floppy disk unit or a data streamer unit for the backup of data stored in a hard disk unit, digital data are recorded on a storage medium such as a floppy disk or a cartridge tape with a format configuration as shown in FIG. 7.
In general, on the magnetic storage media, one or more segments are formed onto each track, and the configuration of one segment on the magnetic storage media is shown in FIG. 7A. One segment is comprised of a header, sectors, and a gap. The header is an area which is used in order to make the data recorded in the sectors are read appropriately. The sectors are areas where the data are recorded. The gap is a blank which separates the next segment.
The header is constructed as shown in FIG. 7B, where the xe2x80x9cGAPxe2x80x9d represents a blank area and the xe2x80x9cSYNCxe2x80x9d represents a synchronizing signal. The xe2x80x9cIAMxe2x80x9d represents an index address mark which indicates the header.
The sector is comprised of an ID portion and a data portion as shown in FIG. 7C. An attribute for the sector is recorded in the ID portion, and data are recorded in the data portion. The xe2x80x9cGAPxe2x80x9d represents a blank area, and the xe2x80x9cSYNCxe2x80x9d represents a synchronizing signal. The xe2x80x9cIDAMxe2x80x9d is an ID address mark which indicates the ID portion, and ID information such as a sector number and the length of the data are recorded in the xe2x80x9cID informationxe2x80x9d area. The xe2x80x9cCRCxe2x80x9d represents a cyclic code which is used for error detection. The xe2x80x9cDAMxe2x80x9d in the data portion represents a data address mark which indicates the data portion, and data are recorded in the xe2x80x9cDATAxe2x80x9d area.
When a data signal is recorded on the magnetic storage medium in the format configuration, the data signal is modulated by a FM method or a MFM method in order to be recorded on the magnetic storage medium.
For one bit of the data signal, the signal is generated in a unit which is called a bit cell. In the FM method, a clock pulse is recorded at the head of each bit cell, and a data pulse is recorded in the middle of each bit cell. In the MFM method, the data pulse is recorded in the middle of each bit cell, and the clock pulse is recorded at the head of the relevant bit cell only when no data are recorded (the data is xe2x80x9c0xe2x80x9d) in the current and present bit cells.
FIG. 8 shows data signals modulated by the FM and MFM methods. With the FM method, the data signal DT shown in FIG. 8A is converted into a recording signal FWS shown in FIG. 8B, where the reference character xe2x80x9cCxe2x80x9d on the recording signal FWS represents the clock pulse and the reference character xe2x80x9cDxe2x80x9d represents the data pulse. With the MFM method, the data signal DT is converted into a recording signal MWS shown in FIG. 8C, where the reference character xe2x80x9cCxe2x80x9d on the recording signal FWS also represents the clock pulse and the reference character xe2x80x9cDxe2x80x9d also represents the data pulse.
With the MFM method, when the time intervals between the bit cells of the recording signal MWS shown in FIG. 8C are shortened by half, the time intervals are equal to those in the FM method, and it is possible to record the data at a density level double that of the FM method. Accordingly, when the digital data are recorded in the high density, the data are generally recorded using the MFM method.
FIG. 9 shows a construction of a conventional magnetic recording storage medium playback apparatus which plays back the data signal from a magnetic storage medium and provides a playback signal. The data signal is recorded at a transmission speed of, for example, 1 megabit/second (the interval between the bit cells=1 xcexcs).
A recording signal WD into which the data signal DT is modulated, is supplied to a flip-flop 1. The flip-flop 1 generates a recording current control signal RC in which the logic level is inverted, synchronized with a rise of the recording signal WD. The recording current control signal RC is supplied to a write amplifier 2. The write amplifier 2 generates a recording current WI based on the recording current control signal RC, which is then supplied to a magnetic head 3. The magnetic head 3 generates a residual flux based on the recording current WI which is recorded on a magnetic storage medium (not shown).
When the magnetic storage medium on which the data signal DT is recorded, is played back, the magnetic storage medium (not shown) is played back using the magnetic head 3, so that a playback signal RS is outputted from a pre-amplifier 4. The playback signal RS is supplied to a differentiator 5, an integrator 6, and a direct current signal generator 7.
The differentiator 5 differentiates the playback signal RS, generating a differentiated signal DRS. In order to correct a peak shift described below, the integrator 6 integrates the playback signal RS in order to provide an integrated signal IRS, and the direct current signal generator 7 generates a direct current signal DCR based on the playback signal RS.
The integrated signal IRS and the direct current signal DCR are supplied to an adder 8, which provides an added signal MID and such signal is provided and is supplied to a subtractor 9. The subtractor 9, upon receiving the differentiated signal DRS from the differentiator 5, subtracts the added signal MID from the differentiated signal DRS to produce a synthesized signal MRS. The synthesized signal MRS is supplied to a zero-volt comparator 10.
The zero-volt comparator 10 outputs the comparison signal CRS at a high level xe2x80x9cHxe2x80x9d when the synthesized signal MRS is above 0 volts, and outputs the comparison signal CRS at a low level xe2x80x9cLxe2x80x9d when the synthesized signal MRS is below 0 volts. The comparison signal CRS is supplied to a pulse shaping circuit 11.
The pulse shaping circuit 11 generates a pulse signal synchronized with an inverted signal level of the comparison signal CRS and provides a read signal RD.
Referring to FIG. 10, the operation of the magnetic storage medium playback apparatus is described below. FIG. 10A shows the recording signal WD. At point t1, when the recording signal WD is increased to the high level H, the recording current control signal RC outputted from the flip-flop 1 shown in FIG. 10B, is inverted from the high level H into the low level L. Based on the recording current control signal RC, the recording current WI at xe2x80x9cxe2x88x92Ixe2x80x9d is supplied to the magnetic head 3 as shown in FIG. 10C so that the signal can be recorded on the magnetic storage medium.
At point t2 after one bit cell period has passed, when the recording signal WD is increased to the high level H, the recording current control signal RC is inverted into the high level H, and the recording current WI at xe2x80x9c+Ixe2x80x9d is supplied to the magnetic head 3 so that the signal is recorded on the magnetic storage medium.
Thereafter, the recording current control signal RC is inverted, synchronized with the inversion of the recording signal WD, and the recording current WI at xe2x80x9cxe2x88x92Ixe2x80x9d or xe2x80x9c+Ixe2x80x9d is supplied to the magnetic head 3 so that the signal can be recorded on the magnetic storage medium.
When the signal recorded on the magnetic storage medium is played back with the magnetic head 3, the playback signal RS shown in FIG. 10D is outputted from the pre-amplifier 4. For example, when a datum at the position on the magnetic storage medium at point t1 is played back, the playback signal RS at point t5 is outputted, and when a datum at the position at point t2, the playback signal RS at point t6 is outputted.
The playback signal RS is supplied to the differentiator 5, where the differentiated signal DRS shown in FIG. 10E is generated. The adder 8 adds the integrated signal IRS from the integrator 6 to the direct current signal DCR from the direct current generator 7 in order to provide the added signal MID shown in FIG. 10F. The subtractor 9 subtracts the added signal MID from the differentiated signal DRS in order to provide a synthesized signal MRS as shown in FIG. 10G.
The synthesized signal MRS is compared with 0 volts in the zero-volt comparator 10. For example, the synthesized signal MRS between points t5 and t6 is above 0 volts, and the comparison signal CRS at the high level H is outputted from the zero-volt comparator 10. Where it is less than 0 volts between points t6 and t7, the comparison signal CRS at the low level L is outputted.
The comparison signal CRS is supplied to the pulse shaping circuit 11, which generates a pulse signal for a predetermined length of time, synchronized with the inversion of the signal level of the comparison signal CRS in order to provide the read signal RD.
When a unit of datum on the magnetic storage medium positioned at point t3 is played back, the peak signal level of the playback signal RS is determined to be the earlier point t8, rather than point t9 which corresponds to point t3 due to the above-described peak shift.
A peak shift is described below with reference to FIG. 11. When the recording signal WD1 shown in FIG. 11A includes only the pulse signal xe2x80x9caxe2x80x9d, the recording current WI1 shown in FIG. 11B is switched from xe2x80x9c+Ixe2x80x9d to xe2x80x9cxe2x88x92Ixe2x80x9d, synchronized with a rise of the pulse signal xe2x80x9caxe2x80x9d, and the signal is recorded on the magnetic storage medium. The playback signal RS1 from the magnetic storage medium which is outputted from the pre-amplifier 4 corresponds to the signal defined by the dashed line xe2x80x9caxe2x80x9d in FIG. 11C.
When the recording signal WD1 includes only the pulse signal xe2x80x9cbxe2x80x9d, the recording current WI1 is switched from xe2x80x9cxe2x88x92Ixe2x80x9d to xe2x80x9c+Ixe2x80x9d, synchronized with a rise of the pulse signal xe2x80x9cbxe2x80x9d, and the signal is recorded on the magnetic storage medium. The playback signal RS1 from the magnetic storage medium corresponds to the signal defined by the dashed line xe2x80x9cbxe2x80x9d.
When the recording signal WD1 includes the pulse signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d, the recording current WI1 is switched from xe2x80x9c+Ixe2x80x9d to xe2x80x9cxe2x88x92Ixe2x80x9d, synchronized with a rise of the pulse signal xe2x80x9caxe2x80x9d, and is thereafter switched from xe2x80x9cxe2x88x92Ixe2x80x9d to xe2x80x9c+Ixe2x80x9d, synchronized with a rise of the pulse signal xe2x80x9cbxe2x80x9d, and the signal is recorded on the magnetic storage medium. The playback signal RS1 from the magnetic storage medium corresponds to the signal defined by the solid line xe2x80x9ccxe2x80x9d over which the signals defined by the dashed lines xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are overlaid. As a result, the peak signal level of the playback signal RS is shifted from point ta (when the playback signal RS includes only the pulse signal xe2x80x9caxe2x80x9d) to point tc, and is shifted from point tb (when the playback signal RS includes only the pulse signal xe2x80x9cbxe2x80x9d) to the point td. Accordingly, when the peak value of the signal level of the playback signal RS is detected from the read signal RD1, the playback signal WD1 cannot be correctly played back because the pulse signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d in the recording signal WD1 shown in FIG. 11D are determined to be pulse signals xe2x80x9caxe2x80x2xe2x80x9d and xe2x80x9cbxe2x80x2xe2x80x9d.
With the MFM method, there are six kinds of signal patterns which cause the peak shift, as shown from FIG. 12A to 12F, where the arrows represent the direction in which the pulse signal is shifted by the peak shift. The time values expressed in the figure are based on a data transmission speed of 1 megabit/second (the interval between the bit cells=1 xcexcs).
The peak shift in the playback signal RS of which the peak signal level is determined at points t8 shown in FIG. 10, is corrected by the calculation of subtracting the added signal MID from the differentiated signal DRS. Accordingly, the synthesized signal MRS is 0 volts at point t9, which corresponds to point t3, so that the read signal RD which is equal to the recording signal WD is obtained. As described above, it is possible to obtain the read signal RD which is equal to the recording signal WD from the playback signal RS by the detection of the peak signal level in the playback signal RS and the peak shift correction.
When the data signal DT is demodulated from the read signal RD, the clock pulse and the data pulse are separated, and a data signal DT is generated, based on the obtained data pulse signal DP. FIG. 13 shows construction of a data separation block for separating the clock pulse and the data pulse from the read signal RD.
In FIG. 13, the read signal RD is supplied to a phase detector 21 in a PLL circuit 20 and to a data separator 30. The phase detector 21 receives a reference clock signal CLK which is outputted from a voltage control oscillator 23 described below, compares the phase of the synchronizing signal in the data signal of the format configuration shown in FIG. 7 with the phase of the reference clock signal CLK, and provides a phase difference signal through a filter 22 to the voltage control oscillator 23. With the voltage control oscillator 23, the frequency of the reference clock signal CLK is controlled using the provided phase difference signal. As described above, the reference clock signal CLK is controlled using the synchronizing signal.
The reference clock signal CLK from the voltage control oscillator 23 is supplied to the data separator 30 which also receives the read signal RD. The reference clock signal CLK is used as a data window signal WP for separating the clock pulse and the data pulse from the read signal RD. The operation of the data separator 30 is described below with reference to FIG. 14.
FIG. 14A shows the read signal RD, in which the reference character xe2x80x9cCxe2x80x9d represents the clock pulse and the reference character xe2x80x9cDxe2x80x9d represents the data pulse. When the data pulse in the read signal RD is supplied to the data separator 30 at point t11, the data pulse is determined to be valid since the data window signal WP (=the reference clock signal CLK) is set to the high level H. When the clock pulse in the read signal RD is supplied to the data separator 30 at point t12, the clock pulse is determined to be invalid since the data window signal WP is set to the low level L. As described above, the data pulse signal DP shown in FIG. 14C is generated from the valid data pulse of the read pulse RD. Further, the data signal DT is generated using the data pulse signal DP.
However, in the circuit which corrects the peak shift of the peak detection signal from the playback signal with the differentiator and the integrator, it is difficult to adjust the differentiator, the integrator, and the direct current signal generator so that the peak shift is appropriately corrected. Further, the correction is easily affected by a change in frequency or in signal level of the playback signal. Moreover, the circuit can not be constructed simply because it requires a differentiator, an integrator, and a direct current signal generator.
The object of the present invention is to provide an improved peak shift correction circuit which can easily correct the peak shift for the peak detection signal from the playback signal from the magnetic storage medium using a simple construction, and an improved magnetic storage medium playback apparatus which can provide the playback digital signal based on the peak detection signal for which the peak shift has been corrected by the peak shift correction circuit.
In one aspect of the present invention, within a peak shift correction circuit, a peak detection means generates a peak detection signal which indicates a peak signal level for a playback signal from a magnetic storage medium. A number of shift register means successively transmit the peak detection signal generated by the peak detection means. A pattern detection means detects a signal pattern of the peak detection signal based on signals from a number of shift register means. A pattern correction means appropriately corrects the time interval in the peak detection signal generated by the peak detection means when the pattern detection means determines that the signal pattern for the peak detection signal corresponds to a signal pattern which causes a peak shift.
Accordingly, a peak detection signal based on a playback signal from a magnetic storage medium is successively transmitted through a number of shift registers. The signal pattern of the peak detection signal is detected by a pattern detection means based on signals outputted from the shift registers and the time interval in the peak detection signal is automatically corrected when the pattern detection means determines that the signal pattern of the peak detection signal corresponds to a signal pattern which causes a peak shift. Accordingly, the peak shift for the peak detection signal is corrected using a simple and inexpensive construction, eliminating a differentiator, an integrator, and a direct current signal generator.
In another aspect of the present invention, within the peak shift correction circuit, the pattern detection means detects one of the signal patterns which cause the peak shift, discriminating between two groups of signal patterns which cause the peak detection signal to shift forward or backward, and the pattern correction means appropriately corrects the time interval in the peak detection signal for each of the groups.
Accordingly, the pattern detection means detects the signal pattern which causes the peak shift, discriminating between two groups of signal patterns which cause the signal to shift forward or backward, and the time interval of the signal is corrected for each group. This makes the construction simple, eliminating the pattern correction blocks for each of the signal patterns which causes the peak shift.
In still another aspect of the present invention, within the peak shift correction circuit, the pattern correction means is provided between a number of shift register means, and appropriately corrects the time interval for the peak detection signal during transmission of the peak detection signal from the peak detection means.
The time interval in the peak detection signal is corrected during transmission of the peak detection signal with the pattern correction means provided between a number of shift register means. Accordingly, the time interval can be corrected without any delay of the peak detection signal.
In yet another aspect of the present invention, the playback signal is modulated using the FM or MFM method in the peak shift correction circuit.
Accordingly, the time interval in the peak detection signal based on the playback signal modulated by the FM or MFM method is corrected. Accordingly, when a data signal modulated by the FM or MFM method is played back from a magnetic storage medium such as a floppy disk, the time interval in the peak detection signal based on the playback signal is also corrected.
In a further aspect of the present invention, the peak shift circuit is used in a magnetic storage medium playback apparatus which has a peak shift correction circuit in a playback signal processing system.
The peak shift correction circuit is used for the playback signal processing system of the magnetic storage medium. Accordingly, the data signal recorded on the magnetic storage medium can be accurately read, and it is possible to provide an inexpensive magnetic storage medium playback apparatus.